The present invention relates to a method for manufacturing an element isolation structural section, particularly, a so-called Shallow Trench Isolation (hereinafter called simply “STI”) which separates a plurality of elements built in a semiconductor substrate from one another.
With developments in a semiconductor micro-fabrication technique, an element isolation method using a conventional LOCOS method is encountering difficulties in building element forming regions (hereinafter also called simply “active regions”) with elements formed therein in thin widths and with satisfactory accuracy. In order to resolve such a problem, a shallow trench has been formed in a semiconductor substrate and element isolation based on an STI with the trench buried by a silicon oxide film has been carried out.
In a film structure removal process employed in an STI manufacturing method, however, a wet etching step has often been performed in general. Due to this wet etching, an unwanted recess called a divot often occurs in the neighborhood of a boundary between the STI and each active region.
When the divot occurs in the STI, for example, a film material for a polysilicon film formed in a gate electrode forming step remains within the divot. In doing so, there is a fear that the electrical characteristic of an element formed in each active region is degraded.
If an attempt is made to remove the film material having remained in the divot, then so-called overetching is carried out. There is however a fear that due to the overetching, for example, a gate oxide film formed in active region is damaged and the electrical characteristic of each element is degraded.
In order to solve such problems of STI associated with the divots, various STI manufacturing methods have been proposed.
There has been known, for example, a method for manufacturing an STI which has a trench having two-stage tapered angles, which is formed on a semiconductor substrate, a thermal oxide film formed in side and bottom faces of the trench, thermal oxide film sidewalls and a CVD oxide film both of which bury the trench, a gate oxide film, and gate polysilicon which covers the gate oxide film, the thermal oxide film sidewalls and the CVD oxide film from above, and wherein the thermal oxide film sidewalls protect upper end portions of the trench from the gate polysilicon (refer to a patent document 1 (Japanese Unexamined Patent Publication No. 2000-022153)).
According to the STI manufacturing process disclosed in the patent document 1, there are no disclosed the formation of a so-called pre-oxide film (sacrifice oxide film) corresponding to processing for cleaning a substrate surface at the formation of the gate polysilicon, its removal, and a height alignment step for allowing the heights of field and active regions immediately before the formation of the gate polysilicon to coincide with each other and planarizing them. Thus, there is a fear that the above problems associated with the divots cannot be resolved even depending on such a manufacturing process.
A problem also arises in that the manufacturing process is complex and the number of manufacturing steps increases.